1. Field of the Invention
The present invention relates to a method and apparatus for reducing skew of signals passing through a memory module. More specifically, the present invention relates to a method and apparatus for reducing the timing skew by adjusting the length of the signal traces on a printed circuit board of the memory module.
2. Description of the Related Art
It is desirable to attempt to eliminate timing skew between signals propagating through high speed memory modules and other types of high speed integrated circuit (xe2x80x9cICxe2x80x9d) modules or circuits. Many techniques have been proposed, but all involve substantial costs, as well as imposing additional manufacturing limitations.
U.S. Pat. No. 5,260,892, for example, describes a method and apparatus for manufacturing an improved Dynamic Random Access Memory (xe2x80x9cDRAMxe2x80x9d) electrical signal interconnect structure having special application to Single In-line Memory Modules (xe2x80x9cSIMMsxe2x80x9d). The structure contains an on-board buffer for deriving time-critical signals from a single source. The conductor structure further includes trace signal routes that allow for approximately equivalent minimum distance signal line lengths. The device further includes vias connecting the front and rear surfaces of the SIMMs, resulting in a high speed, high density SIMM with clean rising and falling edges. The conduction pattern has to be carefully designed and conditioned and is therefore relatively expensive to implement. Moreover, the conductive pattern is fixed and does not allow any type of adjustment to accommodate differences in chip or module performance.
Another method has been proposed in U.S. Pat. No. 5,507,029, which is directed toward a method for minimizing the time skew in very large scale integrated circuits. The method includes equalizing the differences between the early and late mode slack for each of the multi-cycles to decrease the probability of failure. The method further includes maximizing the timing balance between the early and late mode slack, balancing all the net differences between the early and late mode slack, minimizing the statistical variations found within the mode slack pair, and compensating for asymmetries between rising and falling switching times using the mode slack pair. However, this method is also complex and is only concerned with correcting skew between IC chips in a VLSI package, with the ICs being interconnected.
The present invention overcomes the deficiencies in the prior art by providing a method and a structure for reducing timing skew for signals, e.g. clock signals, propagating through a memory module, such as a DRAM, SRAM, or SDRAM memory module. The method is accomplished by adjusting the length of signal traces found on the printed circuit board of the memory module. The signal trace adjustment can be used to reduce timing skew of clock and other module signals, thereby increasing module timing margins and performance.
The present invention also provides for relaxed tolerances in the manufacture of memory modules, with a corresponding reduction in costs, since adjustment of timing skews can be easily accomplished.
The method of the invention includes removing at least one section from at least one printed circuit board trace interconnecting two electrical points or nodes to thereby prevent signals from following the trace and forcing the signals along other traces which interconnect the two nodes.
The apparatus formed by the above method is a printed circuit module board (xe2x80x9cPCBxe2x80x9d) having traces formed thereon as parallel signal paths of differing lengths between two signal nodes with at least one trace being severable to force the signals passing between the two nodes along other signal path traces.